Pass transistor logic is a well known technique to implement complex gates in static logic with a small layout area and a small delay. In order to fully benefit from the higher driving capacitance of NMOS transistors, complementary pass transistor logic can be used. This technique is described in journal article "A 3.8-ns CMOS 16.times.16-b Multiplier Using Complementary Pass-Transistor Logic" by K. Yano et al., in the IEEE Journal of Solid State Circuits, Vol. 25, No. 2, April 1990, pp. 388-395. In this technique, complementary pass transistor logic networks are used to generate in parallel the true and the complement values of logic functions, while inverters are used for buffering the outputs between stages and for ensuring that the signal high level reaches positive supply voltage VDD. However, in this technique, low-to-high transitions through the pass transistor logic network are still in the critical path. Since only NMOS transistors are used in the pass transistor networks, low-to-high transitions propagate slowly through the pass transistor network to the inverter inputs. Moreover, the signal at the inverter input does not reach the potential of the positive supply voltage VDD since the pull-up path contains NMOS transistors with their gates connected to VDD. In this configuration, an NMOS transistor can only pull up a node to (VDD-VTN), where VTN is the threshold voltage of the NMOS transistor. In order to obtain a fast pull-up, specially designed NMOS transistors should be used in the NMOS pass transistor networks, with a threshold voltage close to zero, while the buffering inverters are designed to have a low trip point. Conference article "A 1.5 ns 32b CMOS ALU in Double Pass-Transistor Logic" by M. Suzuki et al., in the IEEE International Solid State Circuits Conference Digest of Technical Papers, February 1993, pp. 90-91, describes how PMOS and NMOS transistors can be used together to obtain a complementary logic network that maintains a high signal level of VDD without requiring buffering, and without requiring specially designed NMOS transistors. However, in this circuit PMOS transistors are reintroduced in the critical path.
It is well known that complex logic functions can be implemented with shorter latency and smaller layout area by using dynamic logic rather than static logic. A well known technique is DOMINO CMOS, described in journal article "High-Speed Compact Circuits with CMOS" by R. Krambeck et al., in the IEEE Journal of Solid State Circuits, Vol. SC-17, No. 3, June 1982, pp. 614-619. This technique employs clocked PMOS transistors for precharging, an NMOS pull-down network having signal inputs and a clock input for discharging, and an inverter for buffering and inverting the output signal. Due to the inversion of the output signal, it is possible to feed the output of such a DOMINO circuit to the input of another DOMINO circuit, and multiple logic levels can be connected for computation during the same evaluation clock phase. DOMINO circuits only use NMOS transistors in their evaluation network, and therefore their layout area and their delay are small. DOMINO logic allows only the implementation of non-inverting logic: only gates that can be reduced to a combination of AND and OR functions can be implemented. In order to generate inverting functions, complementary DOMINO logic must be used. An advantage of DOMINO logic is that it can be used to implement multiple levels of logic during a single evaluation clock phase very quickly, while still maintaining an acceptable noise immunity on intermediate nodes. This is partly due to the use of inverters between logic stages. It is the inverter trip point that determines the noise margin, and not the threshold voltage of individual transistors.
It is known that certain dynamic logic functions such as a carry chain or the bidirectional signal propagation through a path of programmable passive switches can be reliably implemented with a small propagation delay and a small layout area using regenerative feedback circuits or evaluation speed-up circuits at intermediate nodes. The Design and Analysis of VLSI Circuits (L. Glasser and D. Dobberpuhl, Addison-Wesley Publishing Company, Reading, MA, 1985, p. 420, FIG. 8.5) shows a carry chain employing a precharge PMOS transistor and an evaluation circuit with feedback on each intermediate node of the carry chain. Co-pending U.S. patent application Ser. No. 142,900 entitled "DYNAMIC LOGIC INTERCONNECT SPEED-UP CIRCUIT" shows a programmable interconnect architecture employing a precharge PMOS transistor and an evaluation circuit with feedback on intermediate nodes of the interconnect architecture. Such dynamic logic regenerative feedback circuits can be designed to have a good noise immunity on intermediate nodes by letting the node potential at which the feedback loop is turned on be determined by the gate threshold voltage of a logic gate. Also, output signals from a circuit that uses regenerative feedback may be used as the input signals to certain inputs of another circuit that uses regenerative feedback, for computation during the same evaluation clock period.